1. Field of the Invention
The present invention relates to a semiconductor device whose main elements are MOS type field effect transistors (hereinafter referred to as "MOSFET"), and more particularly to a semiconductor memory device in which charging characteristics for column lines can easily be changed in response to changes in the power supply voltage.
2. Description of the Related Art
Generally, in the read only memory element with which the data writing is carried out in a predetermined process step among the fabricating process steps of a semiconductor, there is a memory called a mask ROM (Read Only Memory). In this mask ROM, data is stored by selectively changing a threshold voltage of each of the MOSFETs during the fabrication process.
An N-channel enhancement-mode MOSFET is illustrated in a cross sectional view in FIG. 2 and an N-channel depletion-mode MOSFET is illustrated in a cross sectional view in FIG. 3. In the N-channel enhancement-mode MOSFET shown in FIG. 2, there are a source diffusion layer 32 and a drain diffusion layer 33 on a P-type semiconductor substrate 31 and a gate electrode 34 over a channel region between these diffusion layers. Referring to FIG. 3, in the N-channel depletion-mode MOSFET in which the threshold voltage is negative, there are a source diffusion layer 42 and a drain diffusion layer 43 on a P-type semiconductor substrate 41, a phosphorus diffused channel region 45 formed between the diffusion layers, and a gate electrode 44 formed over the phosphorus diffused channel region 45. Either of the modes, i.e., enhancement-mode or depletion-mode, is selected depending on the kinds of the data to be stored.
The characteristics of the gate voltage versus the drain current of the typical MOSFET are shown in FIG. 4. The N-channel enhancement-mode MOSFET in which the threshold voltage is a positive voltage and has a characteristic curve 51 turns to a conductive state when the gate voltage becomes 1 volt and above. On the other hand, the N-channel depletion-mode MOSFET in which the threshold voltage is a negative voltage and has a characteristic curve 52 turns to a conductive state when the gate voltage becomes -4 volts and above.
During the reading of data from the above memory element, where the gate voltage V.sub.G is 0 volt (V.sub.G =0 V), since the N-channel enhancement-mode MOSFET becomes non-conductive whereas the N-channel depletion-mode MOSFET becomes conductive, the potential of the column line connected to this memory element changes so that it is possible to read the data by detecting a minute voltage change. A sense amplifier circuit operates to detect this minute voltage change.
An example of the conventional semiconductor device as described above has been disclosed in Japanese Patent Application Kokai Publication No. Hei 5-182487.
Of the semiconductor device disclosed in the above publication, the main portion thereof is shown in FIG. 1. As shown in FIG. 1, the sense amplifier and the peripheral circuits are provided with a sense amplifier circuit section SAC consisting of a bias circuit BC1 and a charging circuit CC1, an address transition detecting circuit section (hereinafter referred to as ATD circuit section), and a control circuit section CO1.
The bias circuit BC1 is arranged such that a P-channel MOSFET Q2 as a load element and an N-channel MOSFET Q1 are inserted in series between a power supply terminal V.sub.CC and a column line COLUMN, and the source electrode of the N-channel MOSFET Q1 connected to the column line is also connected to an input terminal of an inverter I1. An output terminal of the inverter I1 is connected to a gate electrode of the N-channel MOSFET Q1 and a sense output SA of the sense amplifier is taken out from the drain electrode of the N-channel MOSFET Q1.
In the charging circuit CC1, an N-channel MOSFET Q3 and an N-channel MOSFET Q4 are inserted between the power supply terminal V.sub.CC and the column line, and the source electrode of the N-channel MOSFET Q4 connected to the column line is also connected to one input terminal of a NOR gate G1. The output terminal of this NOR gate G1 is connected to the gate electrode of the N-channel MOSFET Q4 and the output terminal of the control circuit section CO1 is connected to the other input terminal of the NOR gate G1. The output signal line ATD of the ATD circuit section AA1 is connected to the gate electrode of the N-channel MOSFET Q3.
The control circuit section CO1 is provided with a memory element MC1 which has the same configuration as the read only memory element as shown in FIGS. 2 and 3. The P-channel MOSFET Q7 and the N-channel MOSFET MC1 are inserted between the power supply terminal V.sub.CC and the ground potential terminal V.sub.SS2, and the gate electrodes are connected to the respective source electrodes. The drain electrode of the N-channel MOSFET MC1 is connected to one input terminal of the NOR gate G3 and the inverted signal CEB of a semiconductor device enabling signal (hereinafter referred to as "chip enable signal") is inputted to the other input terminal of the NOR gate G3. The output terminal of the NOR gate G3 is connected to the input terminal of the inverter I3, and the output of the control circuit section CO1 is taken out from the output terminal of the inverter I3 and is supplied to the NOR gate G1.
At the ATD circuit section AA1, output terminals of the address buffers B1-Bm which supply external address signals A1-Am are respectively connected to input terminals of the address transition detecting circuit ATD1, and the output signal line ATD is taken out from an output terminal thereof.
The memory cell block MC is connected such that, for example, memory cells M1-M16 are connected in series between the column line and the ground potential terminal V.sub.SS1.
The sense amplifier circuit and the peripheral circuits having the above construction output data as sense amplifier outputs SA in response to a conductive state or a non-conductive state of the memory cells connected in parallel with the column lines.
Next, the operation of the conventional sense amplifier and the peripheral circuits is explained. First, when the inverted signal CEB of the chip enable signal for enabling the overall semiconductor device, which is applied to one input terminal of the NOR gate G3 of the control circuit CO1 is high in a logical level, that is, when the semiconductor device is in an inactivated state, the output of the NOR gate G3 does not depend on the level of the other input terminal so as to be always low in a logical level, and a high level signal is supplied to the NOR gate G1 as one input signal through the inverter I3.
Thus, since the output of the NOR Gate G1 does not depend on the other input signal and is always at a low level, the N-channel MOSFET Q4 is always in a non-conductive state. That is, it is arranged such that the charging circuit CC1 becomes an inactivated state when the semiconductor device is in the inactivated state.
Next, when the inverted signal CEB of the chip enable signal which is inputted to the NOR Gate G3 as one input signal is at a low level, that is, when the semiconductor device is in an activated state, the output level of the NOR gate G3 is such that it depends on the level of the other input signal (the level at the node N2).
First, when the memory element MC1 is of an N-channel enhancement-mode MOSFET and the semiconductor device is in the activated state, the memory element MC1 is in the inactivated state since the gate electrode thereof is of a ground potential, and one input terminal of the NOR gate G3 receives the signal CEB and the other input terminal thereof receives a high level signal because of the P-channel MOSFET Q7 which functions as a load. For this reason, the output of the NOR gate G3 always becomes a low level without depending on the one input signal CEB so that, when the high level signal is inputted to the NOR gate G1 through the inverter I3, the output of the NOR gate G1 always becomes a low level and the N-channel MOSFET Q4 turns to a non-conductive state, whereby the charging circuit CC1 becomes an inactivated and non-operating state. Thus, the sense amplifier circuit section SAC is caused to be operated solely by the bias circuit BC1.
Next, when the memory element MC1 is of the N-channel depletion-mode MOSFET and the semiconductor device is in an activated state, if the mutual transfer conductance of the memory element MC1 is designed sufficiently large as compared with that of the P-channel MOSFET Q7, one of the input signals applied to the NOR gate G3 becomes a low level. Here, since the signal CEB is also at a low level, the output of the NOR gate G3 becomes a high level, and the signal of a low level is supplied to the NOR gate G1 through the inverter I3.
For the above reason, the charging circuit CC1 becomes an activated state so that, depending on the data inputted to an input node COJ of the bias circuit BC1 which is the other of the inputs to the NOR gate G1, the signal of a high level or a low level is outputted therefrom and, in response thereto, the N-channel MOSFET Q4 turns to either a conductive state or a non-conductive state.
The operation of the sense amplifier circuit section SAC at this time is explained as follows. First, the memory cells selected become conductive, that is, by reference to FIG. 1, the signals X1-X15 supplied to the gate electrodes of the memory cells M1-M15 constituted by the N-channel enhancement-mode MOSFETs are at high levels and the signal X16 supplied to the Gate electrode of the memory cell M16 constituted by the N-channel depletion-mode MOSFET is at a low level, the memory cells all become conductive and, as a consequence, the current flows from the column line to the ground potential terminal V.sub.SS1 through the memory cells and the potential at the input node COJ of the sense amplifier circuit section SAC is discharged and falls.
When the potential at the input node COJ of the sense amplifier circuit section SAC falls below the logical threshold values of the inverter I1 and the NOR gate G1, the outputs of the inverter I1 and the NOR Gate G1 turn to high levels, and both the N-channel MOSFETs Q1 and Q4 become conductive. Therefore, the sense output signal SA of the sense amplifier circuit section SAC is charged by the P-channel MOSFET Q2 functioning as a load and becomes a high level. At this time, if the pulse signal is generated from the ATD circuit section AA1, the N-channel MOSFET Q3 is in a conductive state during the period in which the pulse signal is at a high level, and the column line is charged until the potential at the column line reaches the logical threshold voltages of the inverter I1 and the NOR gate G1 or until the pulse signal becomes a low level.
As explained above, the charging capability of the sense amplifier can be changed depending on whether data is written in the memory element MC1 during the fabrication process. In the semiconductor device in which the sense amplifier circuit and the peripheral circuits having configurations as explained above are used, in the case where the power supply voltage in operation is 5 volts, generally the memory element MC1 employs an N-channel enhancement-mode MOSFET and is optimally designed so that the bias circuit section BC1 operates fast and stably. On the other hand, where the power supply voltage in operation is 3 volts or in a vicinity thereof, the biasing capability of the bias circuit BC1 lowers so that an optimal design for compensating the lowered capability is made such that the memory element MC1 employs the N-channel depletion-mode MOSFET and uses the charging circuit CC1.
The foregoing explanation distinguishes the operation by whether the data has been written in the memory element MC1. However, it is to be understood that the same effect can be attained when the signal supplied from the control circuit section CO1 to the NOR gate G1 is fixed to either the ground potential or the power supply potential.
For fabricating the above described conventional sense amplifier circuit, depending on whether the memory element MC1 employs either the N-channel enhancement-mode MOSFET or the N-channel depletion-mode MOSFET, it is necessary to change the mask patterns used in the lithography step during the fabrication of the semiconductor device. Thus, for the products with the power supply voltage of 5 volts and 3 volts, different masks must be prepared and used during the fabrication. Thus, a problem is that the fabrication requires an increased number of process steps and management steps.
Generally, in the mask ROM, an intermediate product (a product completed up to a step immediately preceding the writing-in of data) is fabricated and, after the data that the customer requires is received, the remaining steps including writing-in of data are carried out. Thus, a problem is that, in the case where the mask patterns are changed before the writing-in of the data, it is necessary that a variety of intermediate products be fabricated and prepared in advance, and this complicates the fabrication process management.
Further, where a mask pattern is used and an optimal value is once set with respect to either of the two different power supply voltages, it is not possible to change the optimal value to the other voltage unless a change is made again in the mask patterns.